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ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
15 years 9 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
HAPTICS
2005
IEEE
15 years 9 months ago
Dynamic Primitive Caching for Haptic Rendering of Large-Scale Models
In this paper we present a software approach to managing complexity for haptic rendering of large-scale geometric models, consisting of tens to hundreds of thousands of distinct g...
Mashhuda Glencross, Roger J. Hubbold, Ben Lyons
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 8 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
WETICE
2009
IEEE
15 years 11 months ago
BitTorrent or BitCrunch: Evidence of a Credit Squeeze in BitTorrent?
Abstract—BitTorrent is a highly popular peer-to-peer filesharing protocol. Much BitTorrent activity takes place within private virtual communities called “Private Trackers” ...
David Hales, Rameez Rahman, Boxun Zhang, Michel Me...
ISHPC
1999
Springer
15 years 8 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan