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ICPADS
2006
IEEE
14 years 1 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
14 years 2 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 2 days ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISCA
1997
IEEE
113views Hardware» more  ISCA 1997»
13 years 12 months ago
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
Richard P. Martin, Amin Vahdat, David E. Culler, T...
CISIS
2008
IEEE
14 years 2 months ago
Latency Impact on Spin-Lock Algorithms for Modern Shared Memory Multiprocessors
In 2006, John Mellor-Crummey and Michael Scott received the Dijkstra Prize in Distributed Computing. This prize was for their 1991 paper on algorithms for scalable synchronization ...
Jan Christian Meyer, Anne C. Elster