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VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
14 years 1 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
GECCO
2005
Springer
135views Optimization» more  GECCO 2005»
14 years 3 months ago
Dynamic optimization of migration topology in internet-based distributed genetic algorithms
Distributed Genetic Algorithms (DGAs) designed for the Internet have to take its high communication cost into consideration. For island model GAs, the migration topology has a maj...
Johan Berntsson, Maolin Tang
ASPDAC
1998
ACM
74views Hardware» more  ASPDAC 1998»
14 years 2 months ago
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines
— Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus li...
Hiroshi Kawaguchi, Takayasu Sakurai
VLSID
2003
IEEE
148views VLSI» more  VLSID 2003»
14 years 10 months ago
Extending Platform-Based Design to Network on Chip Systems
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
ICRA
2000
IEEE
124views Robotics» more  ICRA 2000»
14 years 1 months ago
Design of a Cricket Microrobot
Our goal is to develop an autonomous robot that will fit within a two-inch cube and will locomote by walking and jumping. The robot will be based on the kinematics of a cricket. I...
Matthew C. Birch, Roger D. Quinn, Geon Hahm, Steph...