174 search results - page 33 / 35 » Web-based Distributed VLSI Design |
ISPD
2009
ACM
14 years 4 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ISPD
2004
ACM
14 years 3 months ago
2004
ACM
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
GECCO
2006
Springer
14 years 1 months ago
2006
Springer
Wire routing in a VLSI chip often requires minimization of wire-length as well as the number of intersections among multiple nets. Such an optimization problem is computationally ...
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
SBCCI
2005
ACM
14 years 3 months ago
2005
ACM
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...