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» Wire shaping of RLC interconnects
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ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 4 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
14 years 1 months ago
Inductance extraction for general interconnect structures
As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is d...
Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia...
DSD
2009
IEEE
77views Hardware» more  DSD 2009»
14 years 2 months ago
Pulse Generation for On-chip Data Transmission
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...
Simon Hollis
ISVLSI
2006
IEEE
88views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
Itisha Chanodia, Dimitrios Velenis
DAGSTUHL
2006
13 years 8 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver