25 search results - page 3 / 5 » Wire sizing with scattering effect for nanoscale interconnec... |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
ICCAD
2007
IEEE
13 years 9 months ago
2007
IEEE
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
TVLSI
2002
13 years 7 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...