25 search results - page 4 / 5 » Wire sizing with scattering effect for nanoscale interconnec... |
GLVLSI
2000
IEEE
13 years 11 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
TPDS
1998
13 years 7 months ago
1998
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconn...