94 search results - page 10 / 19 » Wire width planning for interconnect performance optimizatio... |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
TVLSI
2002
13 years 7 months ago
2002
Abstract--The rectilinear Steiner tree (RST) problem is of essential importance to the automatic interconnect optimization for VLSI design. In this paper, we present a class of pro...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present practical algorithms for the synthesis of crosstalk cancelling equalizing filters. We examine designs optimized for the traditional l2 metric and introduce an approach ...