94 search results - page 12 / 19 » Wire width planning for interconnect performance optimizatio... |
MICRO
2003
IEEE
14 years 19 days ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
ERSA
2006
13 years 8 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...