94 search results - page 8 / 19 » Wire width planning for interconnect performance optimizatio... |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
TCAD
2008
13 years 7 months ago
2008
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
ISVLSI
2003
IEEE
14 years 19 days ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...