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» WireMap: FPGA technology mapping for improved routability
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FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
14 years 7 days ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
14 years 5 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
13 years 10 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong
FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
14 years 7 days ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich
DAC
1998
ACM
14 years 24 days ago
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis
Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multipleoutput...
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Hu...