564 search results - page 100 / 113 » Wireplanning in logic synthesis |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tas...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
ASAP
2009
IEEE
14 years 4 months ago
2009
IEEE
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...