564 search results - page 12 / 113 » Wireplanning in logic synthesis |
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...
ICCD
1993
IEEE
14 years 16 days ago
1993
IEEE
for a state machine which is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further ...
IJIT
2004
13 years 9 months ago
2004
This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuit...
DATE
2004
IEEE
14 years 4 days ago
2004
IEEE
As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synt...