Sciweavers

564 search results - page 13 / 113
» Wireplanning in logic synthesis
Sort
View
ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 6 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards
VLSID
1999
IEEE
86views VLSI» more  VLSID 1999»
14 years 20 days ago
Multi-Valued Logic Synthesis
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized ...
Robert K. Brayton, Sunil P. Khatri
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
14 years 2 months ago
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error dete...
Mihir R. Choudhury, Kartik Mohanram
LOPSTR
1997
Springer
14 years 16 days ago
Implicit Program Synthesis by a Reversible Metainterpreter
Synthesis of logic programs is considered as a special instance of logic programming. We describe experience made within a logical metaprogramming environment whose central compone...
Henning Christiansen
CAV
2010
Springer
286views Hardware» more  CAV 2010»
13 years 8 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko