564 search results - page 24 / 113 » Wireplanning in logic synthesis |
ERSA
2006
13 years 9 months ago
2006
Abstract-- We have continued development of Optically Reconfigurable Gate Arrays (ORGAs) to realize larger virtual gate count VLSIs than currently available VLSIs. The grain and st...
AICCSA
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents an encoding algorithm that is very efficient for many different logic synthesis problems. The algorithm is based on the use of special tables and includes two ...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
ICCAD
1997
IEEE
14 years 19 days ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...