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search results - page 29 / 113
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Wireplanning in logic synthesis
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ICCD
2006
IEEE
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Synthesis of Regular Logic Bricks for Robust IC Design
14 years 5 months ago
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iccd.et.tudelft.nl
Kim Yaw Tong, Lawrence T. Pileggi
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ICCAD
2002
IEEE
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Topologically constrained logic synthesis
14 years 5 months ago
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www.eecs.berkeley.edu
Subarnarekha Sinha, Alan Mishchenko, Robert K. Bra...
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17
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ASPDAC
2009
ACM
132
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ASPDAC 2009
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A cycle-based synthesis algorithm for reversible logic
14 years 3 months ago
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Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morte...
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DATE
2008
IEEE
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DATE 2008
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Quantified Synthesis of Reversible Logic
14 years 2 months ago
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Robert Wille, Hoang M. Le, Gerhard W. Dueck, Danie...
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ATVA
2007
Springer
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ATVA 2007
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Distributed Synthesis for Alternating-Time Logics
14 years 2 months ago
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www.csc.liv.ac.uk
Sven Schewe, Bernd Finkbeiner
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