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» Wireplanning in logic synthesis
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ICCD
2006
IEEE
96views Hardware» more  ICCD 2006»
14 years 5 months ago
Synthesis of Regular Logic Bricks for Robust IC Design
Kim Yaw Tong, Lawrence T. Pileggi
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
14 years 5 months ago
Topologically constrained logic synthesis
Subarnarekha Sinha, Alan Mishchenko, Robert K. Bra...
ASPDAC
2009
ACM
132views Hardware» more  ASPDAC 2009»
14 years 3 months ago
A cycle-based synthesis algorithm for reversible logic
Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morte...
DATE
2008
IEEE
81views Hardware» more  DATE 2008»
14 years 2 months ago
Quantified Synthesis of Reversible Logic
Robert Wille, Hoang M. Le, Gerhard W. Dueck, Danie...
ATVA
2007
Springer
127views Hardware» more  ATVA 2007»
14 years 2 months ago
Distributed Synthesis for Alternating-Time Logics
Sven Schewe, Bernd Finkbeiner