564 search results - page 2 / 113 » Wireplanning in logic synthesis |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Logic synthesis systems are complex systems and algorithmic research in synthesis has become highly specialized. This creates a gap where it is often not clear how an advance in a...
ISPD
2012
ACM
12 years 2 months ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
ASYNC
2005
IEEE
14 years 29 days ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
ICFP
2012
ACM
11 years 9 months ago
2012
ACM
The higher-order logic found in proof assistants such as Coq and various HOL systems provides a convenient setting for the development and verification of pure functional program...