564 search results - page 40 / 113 » Wireplanning in logic synthesis |
WCE
2007
13 years 9 months ago
2007
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
ITC
1998
IEEE
14 years 22 days ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
DATE
2000
IEEE
14 years 27 days ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
ATVA
2008
Springer
13 years 10 months ago
2008
Springer
In this paper, a uniform approach for synthesizing monitors checking correctness properties specified in linear-time logics at runtime is provided. Therefore, a generic three-value...