564 search results - page 51 / 113 » Wireplanning in logic synthesis |
EURODAC
1994
IEEE
14 years 19 days ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is ...
DAC
1996
ACM
14 years 20 days ago
1996
ACM
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
GECCO
2006
Springer
14 years 5 days ago
2006
Springer
This poster paper outlines a method for a search based approach to the development of provably correct protocols. Categories and Subject Descriptors C.2.2 [Computer Communication ...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...