564 search results - page 93 / 113 » Wireplanning in logic synthesis |
VLSID
2003
IEEE
14 years 19 days ago
2003
IEEE
With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the ...
FPL
2009
Springer
14 years 6 hour ago
2009
Springer
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
ISSS
1998
IEEE
13 years 11 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We study a new placement problem: the reproducing placement problem (RPP). In each phase a module (or gate) is decomposed into two (or more) simpler modules. The goal is nd a \go...