85 search results - page 5 / 17 » Wiring edge-disjoint layouts |
FPGA
2003
ACM
14 years 25 days ago
2003
ACM
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
ISPD
1998
ACM
13 years 12 months ago
1998
ACM
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...