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ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
14 years 1 months ago
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the p...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Hai...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 1 months ago
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
With power dissipation becoming an increasingly vexing problem across many classes of computer systems, measuring power dissipation of real, running systems has become crucial for...
Canturk Isci, Margaret Martonosi
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 1 months ago
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults
—With the advancement of CMOS manufacturing process to nano-scale, future shipped microprocessors will be increasingly vulnerable to intermittent faults. Quantitatively character...
Songjun Pan, Yu Hu, Xiaowei Li
ECRTS
2002
IEEE
14 years 1 months ago
A QoS-Sensitive Approach for Timeliness and Freshness Guarantees in Real-Time Databases
The demand for real-time database services has been increasing recently. Examples include sensor data fusion, decision support, web information services, and online trading. In th...
Kyoung-Don Kang, Sang Hyuk Son, John A. Stankovic,...
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
14 years 24 days ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith