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DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 4 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
14 years 1 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
FPL
2004
Springer
87views Hardware» more  FPL 2004»
14 years 1 months ago
A Dynamic NoC Approach for Communication in Reconfigurable Devices
A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication i...
Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ah...
FPL
2006
Springer
129views Hardware» more  FPL 2006»
14 years 1 months ago
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
Florian Stock, Andreas Koch