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DAC
2012
ACM
11 years 10 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
ISCA
1994
IEEE
88views Hardware» more  ISCA 1994»
13 years 11 months ago
A Unified Architectural Tradeoff Methodology
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
Chung-Ho Chen, Arun K. Somani
MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
13 years 12 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
Low Static-Power Frequent-Value Data Caches
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
Chuanjun Zhang, Jun Yang 0002, Frank Vahid
ICDCS
2010
IEEE
13 years 9 months ago
CacheCast: Eliminating Redundant Link Traffic for Single Source Multiple Destination Transfers
Due to the lack of multicast services in the Internet, applications based on single source multiple destinations transfers such as video conferencing, IP radio, IPTV must use unica...
Piotr Srebrny, Thomas Plagemann, Vera Goebel, Andr...