1000 search results - page 184 / 200 » Yield-Aware Cache Architectures |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
HT
2006
ACM
14 years 1 months ago
2006
ACM
We present Opal, a light-weight framework for interactively locating missing web pages (http status code 404). Opal is an example of “in vivo” preservation: harnessing the col...
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
In the past, there have been several denial-of-service (DOS) attacks which exhaust some shared resource (e.g., physical memory, process table, file descriptors, TCP connections) ...