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ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 5 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 12 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
DATE
1997
IEEE
86views Hardware» more  DATE 1997»
13 years 12 months ago
Highly scalable parallel parametrizable architecture of the motion estimator
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
Radim Cmar, Serge Vernalde
ANCS
2010
ACM
13 years 5 months ago
A new TCB cache to efficiently manage TCP sessions for web servers
TCP/IP, the most commonly used network protocol, consumes a significant portion of time in Internet servers. While a wide spectrum of studies has been done to reduce its processin...
Guangdeng Liao, Laxmi N. Bhuyan, Wei Wu, Heeyeol Y...
IADIS
2003
13 years 9 months ago
Scalability of Cooperative Algorithms for Distributed Architectures of Proxy Servers
Systems consisting of multiple proxy servers are a popular solution to deal with performance and network resource utilization problems related to the growth of the Web numbers. Af...
Riccardo Lancellotti, Francesca Mazzoni, Michele C...