1000 search results - page 64 / 200 » Yield-Aware Cache Architectures |
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
ISCAS
2002
IEEE
14 years 22 days ago
2002
IEEE
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...