1000 search results - page 69 / 200 » Yield-Aware Cache Architectures |
CSREAESA
2006
13 years 10 months ago
2006
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
MIDDLEWARE
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. Edge-server architectures are widely used to improve webapplication performance for non-transactional data. However, their use with transactional data is complicated by t...
DATAMINE
2000
13 years 8 months ago
2000
Data mining on large data warehouses is becoming increasingly important. In support of this trend, we consider a spectrum of architectural alternatives for coupling mining with da...
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...