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» Yield-driven iterative robust circuit optimization algorithm
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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 4 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
ADAC
2008
193views more  ADAC 2008»
13 years 7 months ago
A constrained-optimization based half-quadratic algorithm for robustly fitting sets of linearly parametrized curves
We consider the problem of multiple fitting of linearly parametrized curves, that arises in many computer vision problems such as road scene analysis. Data extracted from images us...
Jean-Philippe Tarel, Sio-Song Ieng, Pierre Charbon...
ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
13 years 12 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
13 years 9 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ISQED
2005
IEEE
119views Hardware» more  ISQED 2005»
14 years 1 months ago
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fa...
Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, ...