215 search results - page 9 / 43 » Yield-driven iterative robust circuit optimization algorithm |
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
Recent research has revealed that circularity (or, propriety) of complex random signals can be exploited in developing optimal signal processors. In this paper, a robust estimator...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
PRL
2010
13 years 6 months ago
2010
We consider the problem of fitting linearly parameterized models, that arises in many computer vision problems such as road scene analysis. Data extracted from images usually cont...