32 search results - page 4 / 7 » Zero-cycle loads: microarchitecture support for reducing loa... |
NOCS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
ANCS
2008
ACM
13 years 10 months ago
2008
ACM
The amount of intelligent packet processing in an Ethernet switch continues to grow, in order to support of embedded applications such as network security, load balancing and qual...
HPCA
2004
IEEE
14 years 9 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
HIPEAC
2007
Springer
14 years 2 months ago
2007
Springer
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
ISCA
1995
IEEE
14 years 3 days ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...