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GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISCA
2010
IEEE
240views Hardware» more  ISCA 2010»
15 years 9 months ago
Modeling critical sections in Amdahl's law and its implications for multicore design
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
Stijn Eyerman, Lieven Eeckhout
SSDBM
2010
IEEE
117views Database» more  SSDBM 2010»
15 years 9 months ago
Finding Top-k Similar Pairs of Objects Annotated with Terms from an Ontology
With the growing focus on semantic searches and interpretations, an increasing number of standardized vocabularies and ontologies are being designed and used to describe data. We ...
Arnab Bhattacharya, Abhishek Bhowmick, Ambuj K. Si...
124
Voted
CF
2010
ACM
15 years 9 months ago
EXACT: explicit dynamic-branch prediction with active updates
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a...
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg