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ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 5 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 5 months ago
Robust analog/RF circuit design with projection-based posynomial modeling
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence ...
ICCAD
2004
IEEE
83views Hardware» more  ICCAD 2004»
14 years 5 months ago
Custom-optimized multiplierless implementations of DSP algorithms
Linear DSP kernels such as transforms and filters are comprised exclusively of additions and multiplications by constants. These multiplications may be realized as networks of ad...
Markus Püschel, Adam C. Zelinski, James C. Ho...
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 5 months ago
Static statistical timing analysis for latch-based pipeline designs
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, San...
ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
14 years 5 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu