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DAC
1996
ACM
14 years 20 days ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
DAC
1996
ACM
14 years 20 days ago
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
Jason Cong, Yean-Yow Hwang
DAC
1996
ACM
14 years 20 days ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
DAC
1996
ACM
14 years 20 days ago
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
V. Chandramouli, Karem A. Sakallah
DAC
1996
ACM
14 years 20 days ago
A Sparse Image Method for BEM Capacitance Extraction
Boundary element methods (BEM) are often used for complex 3-D capacitance extraction because of their efficiency, ease of data preparation, and automatic handling of open regions. ...
Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T....