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DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 1 months ago
An event-guided approach to reducing voltage noise in processors
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. H...
DATE
2003
IEEE
79views Hardware» more  DATE 2003»
14 years 1 days ago
Time Budgeting in a Wireplanning Context
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. ...
COLING
2000
13 years 8 months ago
Data-Oriented Translation
Data-Oriented Translation (DOT), which is based on Data-Oriented Parsing (DOP), comprises an experience-based approach to translation, where new translations are derived with refe...
Arjen Poutsma
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
14 years 1 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 1 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek