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2000
IEEE
113views Hardware» more  DATE 2000»
13 years 11 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
13 years 11 months ago
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2000
IEEE
111views Hardware» more  DATE 2000»
13 years 11 months ago
Static Timing Analysis Taking Crosstalk into Account
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
Matthias Ringe, Thomas Lindenkreuz, Erich Barke
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
13 years 11 months ago
Assessing the Cost Effectiveness of Integrated Passives
Passive components integrated into a high-density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted onto the system board. Sti...
Michael Scheffler, Gerhard Tröster
DATE
2000
IEEE
137views Hardware» more  DATE 2000»
13 years 11 months ago
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr