- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
: The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the...
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...