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ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A 52mW 1200MIPS compact DSP for multi-core media SoC
- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting ...
MJ
2006
145views more  MJ 2006»
13 years 7 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
IAJIT
2010
150views more  IAJIT 2010»
13 years 6 months ago
Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder
: The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the...
Imen Werda, Haithem Chaouch, Amine Samet, Mohamed ...
IPPS
2006
IEEE
14 years 1 months ago
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
Kostas Siozios, Konstantinos Tatas, Dimitrios Soud...
IPPS
2006
IEEE
14 years 1 months ago
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...