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GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Information storage capacity of crossbar switching networks
In this work we ask the fundamental question: How many bits of information can be stored in a crossbar switching network? The answer is trivial when the switches of the network ar...
Paul-Peter Sotiriadis
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
14 years 3 months ago
A novel 32-bit scalable multiplier architecture
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
Yeshwant Kolla, Yong-Bin Kim, John Carter
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann