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ICCAD
2005
IEEE
70views Hardware» more  ICCAD 2005»
14 years 4 months ago
Physics-based compact modeling for nonclassical CMOS
Physics-based compact modeling, as opposed to the conventional empirical approach, is emphasized for nanoscale nonclassical CMOS. UFDG, a physics-based compact model for generic d...
Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Mu...
ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
14 years 7 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 7 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 7 months ago
Statistical timing analysis with two-sided constraints
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
Khaled R. Heloue, Farid N. Najm
ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
14 years 7 months ago
Performance analysis of carbon nanotube interconnects for VLSI applications
The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this ...
Navin Srivastava, Kaustav Banerjee