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ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 4 months ago
Boolean factoring and decomposition of logic networks
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut based view of a logic network, 2) exploiting th...
Alan Mishchenko, Robert K. Brayton, Satrajit Chatt...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 4 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
14 years 4 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
ICCAD
2008
IEEE
80views Hardware» more  ICCAD 2008»
14 years 4 months ago
Advancing supercomputer performance through interconnection topology synthesis
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
Yi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan...
ICCAD
2008
IEEE
84views Hardware» more  ICCAD 2008»
14 years 4 months ago
A voltage-frequency island aware energy optimization framework for networks-on-chip
— In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (Voltage-Frequency Island) based Network-on-Chip. Unlike the rece...
Wooyoung Jang, Duo Ding, David Z. Pan