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DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 1 months ago
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperat...
José Luis Rosselló, Vicens Canals, S...
CHES
2005
Springer
129views Cryptology» more  CHES 2005»
14 years 1 months ago
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment
Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results sh...
Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng L...
ICCD
2005
IEEE
124views Hardware» more  ICCD 2005»
14 years 4 months ago
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
ISCAS
2007
IEEE
125views Hardware» more  ISCAS 2007»
14 years 1 months ago
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples
—This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transc...
S. P. Voinigescu, S. T. Nicolson, M. Khanpour, K. ...
ESWA
2007
105views more  ESWA 2007»
13 years 7 months ago
Applying rough sets to prevent customer complaints for IC packaging foundry
Packaging is classified as one of back-end processes in the integrated circuits (ICs) manufacturing, highly capital-intensive and involves complex processes. Unlike the front-end...
Hsu-Hao Yang, Tzu-Chiang Liu, Yen-Ting Lin