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ASPDAC
2009
ACM
160views Hardware» more  ASPDAC 2009»
14 years 2 months ago
CAD challenges for 3D ICs
David S. Kung, Ruchir Puri
ICCAD
2009
IEEE
129views Hardware» more  ICCAD 2009»
13 years 8 months ago
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
14 years 5 months ago
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
— Negative Bias Temperature Instability (NBTI) is a leading reliability concern for integrated circuits (ICs). It gradually increases the threshold voltages of PMOS transistors, ...
Lide Zhang, Robert P. Dick
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
14 years 5 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
CHES
2009
Springer
248views Cryptology» more  CHES 2009»
14 years 11 months ago
The State-of-the-Art in IC Reverse Engineering
? This paper gives an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products. Th...
Randy Torrance, Dick James