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CORR
2002
Springer
93views Education» more  CORR 2002»
13 years 10 months ago
Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
Denis V. Popel
VTS
2002
IEEE
101views Hardware» more  VTS 2002»
14 years 3 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
14 years 3 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
DAC
2002
ACM
14 years 11 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
ATS
2002
IEEE
118views Hardware» more  ATS 2002»
14 years 3 months ago
Diagnosis Of Byzantine Open-Segment Faults
This paper addresses the problem of locating the stuckopen faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty s...
Shi-Yu Huang