-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
This paper addresses the problem of locating the stuckopen faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty s...