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ISLPED
2005
ACM
119views Hardware» more  ISLPED 2005»
14 years 2 months ago
FinFET-based SRAM design
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...
Zheng Guo, Sriram Balasubramanian, Radu Zlatanovic...
ISLPED
2005
ACM
123views Hardware» more  ISLPED 2005»
14 years 2 months ago
Coordinated, distributed, formal energy management of chip multiprocessors
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...
ISLPED
2005
ACM
99views Hardware» more  ISLPED 2005»
14 years 2 months ago
A low-power bus design using joint repeater insertion and coding
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
Srinivasa R. Sridhara, Naresh R. Shanbhag
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 2 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
14 years 2 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang