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ISQED
2007
IEEE
119views Hardware» more  ISQED 2007»
14 years 1 months ago
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
Abstract— Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon [2], [4], [8]. So far, reliable op...
Frederic Worm, Patrick Thiran, Paolo Ienne
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
14 years 1 months ago
Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems
— In the past, dynamic voltage and frequency scaling (DVFS) has been widely used for power and energy optimization in embedded system design. As thermal issues become increasingl...
Yongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wa...
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
14 years 1 months ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
14 years 1 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...
ISQED
2007
IEEE
97views Hardware» more  ISQED 2007»
14 years 1 months ago
Probabilistic Congestion Prediction with Partial Blockages
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachi...