This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
James F. Plusquellic, Donald M. Chiarulli, Steven ...
While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. ...
Thomas W. Williams, Robert H. Dennard, Rohit Kapur...
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin...