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VTS
2003
IEEE
14 years 3 months ago
2003
IEEE
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that runlength c...