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ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 3 months ago
Impact of Multiple-Detect Test Patterns on Product Quality
This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizi...
Brady Benware, Chris Schuermyer, Sreenevasan Ranga...
ITC
2003
IEEE
181views Hardware» more  ITC 2003»
14 years 3 months ago
Latch Divergency In Microprocessor Failure Analysis
This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Dive...
Peter Dahlgren, Paul Dickinson, Ishwar Parulkar
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
14 years 3 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 3 months ago
Deformations of IC Structure in Test and Yield Learning
This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Tr...
Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Tho...
ITC
2003
IEEE
147views Hardware» more  ITC 2003»
14 years 3 months ago
The Testability Features of The ARM1026EJ Microprocessor Core
The DFT and Test challenges faced, and the solutions applied, to the ARM1026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the...
Teresa L. McLaurin, Frank Frederick, Rich Slobodni...