Sciweavers

71 search results - page 7 / 15
» nocs 2007
Sort
View
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
15 years 10 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind
ITNG
2007
IEEE
15 years 10 months ago
On the Physicl Layout of PRDT-Based NoCs
In this paper, we present PRDT(2, 1), a new interconnection network topology for Network-on-chip (NoC) design. PRDT(2,1) features a recursive structure, and has small diameter and...
Guoqiang Yang, Mei Yang, Yulu Yang, Yingtao Jiang
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
15 years 10 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 10 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
ICPP
2007
IEEE
15 years 10 months ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...