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2007
IEEE
13 years 10 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 2 months ago
Toward a scalable test methodology for 2D-mesh Network-on-Chips
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
Kim Petersén, Johnny Öberg
DSD
2007
IEEE
86views Hardware» more  DSD 2007»
14 years 2 months ago
On network-on-chip comparison
— This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are curre...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
14 years 5 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
IJPP
2007
56views more  IJPP 2007»
13 years 8 months ago
Fault-aware Communication Mapping for NoCs with Guaranteed Latency
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng